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Extra info for Advanced Xilinx Fpga Design With Ise
What is the difference between the VHO/VEO files and the VHD/V files that are created by the CORE Generator™ system? CORE Generator System - 9 - 26 © 2003 Xilinx, Inc. All Rights Reserved Answers • What is the main difference between the LogiCORE and the AllianceCORE products? exe? – • LogiCORE products are sold and supported by Xilinx AllianceCORE products are sold and supported by AllianceCORE partners Makes it easy to compile the XilinxCoreLib library before your first behavioral simulation What is the difference between the VHO/VEO files and the VHD/V files that are created by the CORE Generator™ system?
All Rights Reserved High Fanout: Solutions • Most likely solution is to duplicate the source of the high-fanout net – – In this example, the net is the output of a flip-flop, so the solution is to duplicate the flip-flop If the net is driven by combinatorial logic, it may be more difficult to locate the source of the net in the HDL code Timing Closure with Timing Analyzer - 19 © 2003 Xilinx, Inc. 7% route) © 2003 Xilinx, Inc. All Rights Reserved Too Many Logic Levels: Solutions • • • The implementation tools cannot do much to improve performance The netlist must be altered to reduce the amount of logic between flip-flops Possible solutions: – Check whether the path is a multi-cycle path • – – – If it is, add a multi-cycle path constraint Use the retiming option during synthesis to distribute logic more evenly between flip-flops Confirm that good coding techniques were used to build this logic (no nested IF or CASE statements) Add a pipeline stage Timing Closure with Timing Analyzer - 21 © 2003 Xilinx, Inc.
All Rights Reserved Lab Design: Correlate and Accumulate CORE Generator System - 9 - 33 © 2003 Xilinx, Inc. All Rights Reserved Channel FIFO Block CORE Generator System - 9 - 34 © 2003 Xilinx, Inc. All Rights Reserved Lab Overview • • • Generate a dual-port block RAM core Replace an instantiated library primitive with the core Perform behavioral simulation on the design – Testbench file provided CORE Generator System - 9 - 35 © 2003 Xilinx, Inc. All Rights Reserved General Flow Step 1: Review the design Step 2: Generate the core Step 3: Instantiate block RAM core into Verilog or VHDL source Step 4: Perform behavioral simulation CORE Generator System - 9 - 36 © 2003 Xilinx, Inc.